1. Field of the Invention
The invention generally relates to PLL (Phase Locked Loop) devices that may operate as frequency synthesizers in communication systems such as WLAN (Wireless Local Area Network) systems, and to WLAN receivers or transceivers and integrated circuit chips. The invention relates, in particular, to PLL devices comprising a prescaler.
2. Description of the Related Art
A wireless local area network is a flexible data communication system implemented as an extension to, or as an alternative for, a wired LAN. Using radio frequency or infrared technology, WLAN (Wireless Local Area Network) systems transmit and receive data over the air, minimizing the need for wired connections. Thus, WLAN systems combine data connectivity with user mobility.
Most WLAN systems use spread spectrum technology, a wide-band radio frequency technique developed for use in reliable and secure communication systems. The spread spectrum technology is designed to trade-off bandwidth efficiency for reliability, integrity and security.
PLL devices are widely used in the above-mentioned technologies for the purpose of frequency synthesis, clock generation, clock recovery, demodulation and others in digital, as well as, in analog based circuits. In frequency synthesis techniques, phase locked loops represent the dominant method in wireless communication systems such as WLAN systems.
Current PLL integrated circuits are able to execute all PLL functions on a single, highly integrated digital and mixed signal circuit that operates on low supply voltages and consumes very low power. These integrated circuits require only an external frequency reference, voltage control oscillators (VCO) and a few external passive components to generate the wide range of frequencies.
An example of a conventional PLL frequency synthesizer is depicted in FIG. 1. As can be seen from the figure, the PLL frequency synthesizer has a forward signal path that includes a phase or frequency detector 150, a loop filter 140, a voltage controlled oscillator 130, and a feedback path that includes a prescaler unit 110 and a divider unit 120. In addition, a swallow counter 100 is provided for controlling the prescaler 110 dependent on a loadable counter factor M. The prescaler output is connected to the swallow counter 100 for synchronizing the swallow counter with a PLL clock. The swallow counter is further connected to a prescaler mode control terminal of the prescaler to provide a mode control signal for controlling the prescaler mode. Beside the divider 120, the prescaler 110 drives the swallow counter 100.
As explained above, the conventional PLL feedback path comprises two separate units having different division factors, and a swallow counter receiving the loadable counter factor M. The prescaler 110 applies a divider factor of P or P+1 depending on the mode control signal delivered by the swallow counter 100. The divider unit 120 applies a fixed divider factor N. The overall divider factor can then be expressed as:X=P·(N−M)+(P+1)·M 
Conventional PLL systems have numerous disadvantages because interference and signal-to-noise ratio are important points to be considered in system design. Phase noise and spurious emissions contribute significantly to signal interference and signal-to-noise ratio and are largely dependent on the performance of the PLL devices.
Phase noise and spurious emissions may appear by toggling the mode of the prescaler 110 in the conventional PLL circuit of FIG. 1. The time chart of FIG. 2 illustrates the toggling of the prescaler mode that is under control of the swallow counter 100. Further, the current consumption behavior of the prescaler 110 is illustrated in correspondence to the depicted mode toggling of the prescaler mode. It can be seen that each toggling of the prescaler 110 effects a high current peak. Those high current peaks may lead to the above-mentioned phase noise and spurious emissions, and the phase noise and spurious emissions are highly disadvantageous.
Thus, minimizing phase noise and spurious emissions of the device is one of the problems of present technologies which is intensely addressed.
An example of a synthesizer where the influences of disturbances are minimized is published in W. Rhee et al. “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order ΔΣ Modulator”, IEEE J. Solid-State Circuits, vol. 35, no 10, October 2000, pp. 1453–1459. However, this approach requires a number of interconnected subunits which are difficult to implement so that the resulting frequency synthesizer is complicated in construction.
An arrangement avoiding the use of a swallow counter is published in T. Kim et al. “Swallow Counterless DMP PLL”, IEEE, VL-P23, 1999, 0-7803-5727-2/99, pp. 606–608. In this technique, the swallow counter is replaced by a JK-flip flop for reducing power consumption and gate counts. However, the described technique may still suffer from the disturbances mentioned above, including those which are related with phase noise and spurious emissions.